Skip to main content
Home/Explainers/Sub-3 nm substrates
EXPLAINER · SEMICONDUCTORS

Sub-3 nm: why deposition substrates now care about roughness

Semiconductor manufacturing at 3 nm and below places substrate-roughness requirements an order of magnitude tighter than their 7 nm predecessors. Nickel substrates — and the purity of the underlying material — move from a process-engineering footnote to a yield-critical input.

GTX Research · Semiconductor desk20 April 202610 minCC-BY-4.0

Why 3 nm is a step-change

Through 28 nm and 16 nm nodes, substrate-roughness requirements were dominated by lithography depth-of-focus. Ra values up to 3 nm on a deposition substrate were absorbed by the patterning process. At 7 nm, EUV lithography tightened the budget. At 3 nm and 2 nm, where gate-all-around (GAA) nanosheet architectures replace finFET, any roughness at the substrate level couples directly into nanosheet thickness variation — which couples into threshold voltage variation — which couples into binning yield[1].

The specification

At sub-3 nm nodes, typical substrate-roughness budgets run: Ra < 1.0 nm across the reticle, with per-die variance < 0.3 nm. For a nickel-containing deposition tool (e.g. certain physical-vapor deposition chucks, electroforming masters), the incoming nickel substrate roughness must be Ra < 1.0 nm before polishing — which cascades back to an upstream wire-drawing tolerance.

Fig. 1 — Surface roughness Ra, as-drawn nickel substrate. Lower is better. Source: partner foundry qualification 2025.

Why purity couples into roughness

Surface roughness on a drawn metal wire is dominated by die-wear and inclusion drag. Inclusions — sulphide, oxide, copper phases — are the single largest source of localised die-wear. At 99.8 % purity, inclusions are at the ~2000 ppm level (2 g per kg of metal); at 99.99 % they are at ~100 ppm (100 mg per kg). The factor-of-20 reduction in inclusion load translates directly to a factor-of-3–4 reduction in drawn-surface Ra.

3D chip-packaging interconnects

Beyond the substrate question, sub-3 nm nodes are typically packaged using advanced 3D stacking (e.g. TSMC CoWoS, Intel Foveros). The through-silicon and through-mould interconnects in those packages use high-purity copper or nickel-capped via stacks. Nickel cap layers at 99.99 % purity offer electromigration resistance that is measurably better than commercial nickel, with MTTF improvements of 2–3× at commercial current densities[2].

Implications for GTX supply

Per-wafer nickel consumption is small in absolute terms (grams), but the specification step from Class-1 to NP1 is non-trivial — few vendors offer NP1-drawn product with auditable chain-of-custody. The structural premium in this segment of the market is therefore less about volume and more about qualification depth.

Sources & references

  1. SEMI World Fab Forecast — 2025 Q2 Update. semi.org
  2. IEDM 2024 Proceedings, Interconnect Reliability session.
  3. ITRS 2.0 / IRDS roadmap projections for sub-3 nm process nodes.